In application specific integrated circuit (ASIC) and rapid circuit design flows, a high number of engineering change orders (ECOs) (i.e., changes to a netlist, inserting buffers and resizing buffers) are commonly used to fix timing or signal integrity related problems close to an end of the design flow. As the implementation of each ECO can easily take up to several days, the high number of ECOs makes accurate project scheduling difficult and therefore unacceptable. A problem in generating the ECOs is that different conventional tools used to do the job do not correlate well to each other. The inaccuracies in correlation often result in a second iteration to the ECOs as the first ECOs do not solve the addressed issue completely. As cell sizes, and therefore cell locations, can change dramatically between the two iterations of the ECOs, results are hard to predict and often leave timing or signal integrity violations unresolved. Also, since cells are displaced relative to each iteration, an effort to reroute the connected signals is very high and can create unforseen congestion.
A conventional approach for dealing with a large number of ECOs is to be pessimistic and add more margin than necessary to the ECO calculations. However, adding more margin to ECO calculations can lead to congestion problems as too many new cells would be inserted into the design. Severe congestion can make the design layout unroutable. In addition, the iteration solution does not guarantee that timing and signal integrity violations will really be fixed. Adding more cells to the design can cause even more displacement of the existing cells and therefore generate new problems.
Another conventional approach is to accept a schedule delay and run several ECOs in a row until all violations are fixed. The conventional solution to run several ECOs in a row is unacceptable because of the long tool runtimes for each of the ECOs. In addition, new routing introduced by each sequential ECO can cause problems at the very end of the design flow, further complicating project scheduling.